The invention is generally related to the field of CMOS transistors and more specifically to a sidewall process for a CMOS transistor.
As semiconductor devices are scaled to smaller dimensions, generally in the sub-0.1 xcexcm region, it becomes more difficult to fabricate transistors with high drive current and small short-channel effects (i.e., reduced threshold voltage roll-off). To this end, pocket implant processes have been implemented to reduce the threshold voltage (Vt) rolloff, reduce the nominal Vt, and thus improve the nominal drive current. The pocket implant process is a process whereby a region of dopants (referred to herein as a pocket region) opposite to the type used for source/drain (and/or source/drain extension) regions is formed adjacent to the source/drain (and/or source/drain extension) regions. The lateral extent of the pocket region is typically less than the channel length of the MOSFET such that the formation of the pocket results in a laterally non-uniform dopant region from the source and/or drain and/or drain extension to the interior of the channel region. While the pocket implant may reduce short-channel effects, it may also increase the channel surface doping nearest the drain extension (and/or source extension) tip to a significant lateral extent to the interior of the channel region. This, in turn, lowers surface mobility due to dopant scattering. So, while drive current is improved by the pocket implant due to lower nominal Vt, the drive current is not as improved as it could be due to enhanced dopant scattering.
Additionally, source and/or drain extension region (referred to hereafter as xe2x80x9cdrain extension regionxe2x80x9d) doping processes have been implemented to reduce the source and/or drain extension region parasitic resistance and to reduce the Vt rolloff and thus improve the nominal drive current. To achieve both low parasitic resistance and low Vt rolloff, the drain extension regions should be of sufficient junction depth to allow for low parasitic resistance but with small gate overlap of the drain extension regions.
It is desired therefore to provide for a structure with improved pocket implant process for high drive current. It is additionally desired to have a structure allowing for use of moderate drain extension implant energies for formation of drain extension regions which have low parasitic resistance with sufficiently low gate overlap of the drain extension regions.
A transistor and method for forming a transistor using an edge blocking material is disclosed herein. The edge blocking material may be located adjacent a gate or disposable gate or may be part of a gate or disposable gate. During an angled pocket implant, the edge blocking material limits the implant range of dopants to be less than that in the semiconductor body and the dopant placed under the edge blocking material is in part located at a given distance below the surface of the semiconductor body. The edge blocking material in part may limit the portion of the angled pocket implant that penetrates through a gate electrode to the underlying channel region in the semiconductor body.
An advantage of the invention is providing a transistor having reduced short channel effects as well as improved surface mobility due to a pocket placed with peak doping below the surface of the channel and/or due to a reduced length of high pocket doping at the channel surface extending laterally from the drain extension regions inwards to the channel region.
Another advantage of the invention is providing a transistor having reduced gate-to-drain and gate-to source capacitance.
Another advantage of the invention is providing a method of forming a transistor using a sidewall spacer that is relatively insensitive to clean-up processes.
These and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.